1. Field of the Invention
The invention relates to a method of fabricating contact holes on a semiconductor chip, and more particularly, to a method only requiring a single photomask to fabricate bit line contact (CB) holes, substrate contact (CS) holes, and gate contact (CG) holes in an array area and a periphery area of a semiconductor chip.
2. Description of the Prior Art
Dynamic random access memory (DRAM) has become a key element of most electronic products. There are a large number of memory cells integrated to form an array area in a DRAM for storing information. The DRAM also comprises a periphery area for locating periphery controlling circuits. Each of the memory cells and the periphery controlling circuits comprises a metal oxide semiconductor (MOS) transistor and other electrical elements, such as a capacitor, in series. The MOS transistor is electrically connected to a word line while the capacitor is electrically connected to a bit line; together, they determine the address of a memory cell. For electrically connecting these electrical elements, contact holes are formed between various material layers so that subsequently formed conductive materials can be filled into the contact holes to complete the functionality of the MOS transistor.
Please refer to FIGS. 1-3, which are schematic diagrams of fabricating contact holes on a semiconductor chip 10 according to the prior art. The semiconductor chip 10 has a substrate 12, and the substrate 12 comprises an array area 14 and a periphery area 16. The array area 14 is used for locating each memory cell of a DRAM and has two gates 18, 20. The periphery area 16 is used for locating the periphery controlling circuits of the DRAM, which has a gate 22. Each of the gates 18, 20, 22 comprises an oxide layer (not shown), a conductive layer 24, a silicide layer 26, a mask layer 28, and a spacer 30. In a conventional method of fabricating the contact holes, a dielectric layer 32 is first deposited on the gates 18, 20, 22, and then, a doped polysilicon layer 34 is deposited on the dielectric layer 32 for being a hard mask of a following etching process. As shown in FIG. 2, a photoresist layer (not shown) is deposited on the doped polysilicon layer 34, and a first photomask CT is used to perform a photolithography-etching process (PEP) to remove a portion of the doped polysilicon layer 34 and the dielectric layer 32. Therefore, a bit line contact hole 36 is formed in the array area 14, and a gate opening 38 and a substrate contact hole 40 are simultaneously formed in the periphery area 16. Referring to FIG. 3, a second PEP is performed by using a second photomask CK to remove the mask layer 28 exposed by the gate opening 38, and thereby a gate contact hole 42 is formed. Then, a glue layer and a metal layer (not shown) are deposited, and an etchback process is performed to fill the metal layer into the bit line contact hole 36, the gate contact hole 38, and the substrate contact hole 40. Thus, subsequently formed elements and conductive lines can be electrically connected to the substrate 12 and the gate 22 through these contact holes.
In the prior art, when fabricating the bit line contact hole 36 of the array area 14 and the gate contact hole 42 and the substrate contact hole 40 of the periphery area 16, it is necessary to use two photomasks CT and CK and perform two photolithography processes, so that the whole fabricating process of these contact holes is very complicated and costs much money and time. In addition, it is a disadvantage to perform the photolithography process to the photoresist layer above the doped polysilicon layer 34, which is taken as a hard mask, according to the prior art. This is because the optical reflection of the doped polysilicon layer 34 is high and the contact holes have a high aspect ratio so that the photoresist layer may remain in the inter-gate space to cause contact holes to have defects, such as voids. Furthermore, the aspect ratio will become even higher as the integration is higher, resulting in the probability of voids occurring being much higher and reducing the yield of products.
It is therefore a primary objective of the claimed invention to provide a method of simultaneously fabricating bit line contact holes, substrate contact holes, and gate contact holes with low aspect ratio in an array area and a periphery area by a single photomask CT to solve the abovementioned problem.
According to the claimed invention, a method of fabricating contact holes on a semiconductor chip is disclosed. The semiconductor chip has a substrate comprising an array area for locating each memory cell of a DRAM and a periphery area for locating a periphery controlling circuit of the DRAM, wherein the array area and the periphery area contain at least a first gate and a second gate respectively. Each of the first gate and second gate comprises a first mask layer on a top surface and a spacer on a sidewall. The method comprises filling a dielectric layer into the inter-gate space of two gates; polishing, for example, using a chemical mechanical polishing process, the dielectric layer until the surface of the dielectric layer is coplanar with the top surface of the gates; depositing a second mask layer; etching the second mask layer to form a bit line opening in the array area and simultaneously forming a gate opening and a substrate opening in the periphery area; etching the dielectric layer through the bit line opening and the substrate opening until the substrate is exposed to form a bit line contact hole and a substrate contact hole; filling a metal layer into the bit line contact hole and the substrate contact hole; and etching the first mask layer through the gate opening to form a gate contact hole.
It is an advantage of the claimed invention that the method only uses a single photomask and one photolithography process to define the pattern of the bit line contact hole, gate contact hole, and the substrate contact hole, so that a total cost of the process can be reduced. In addition, the contact holes fabricated according to the claimed invention have a lower aspect ratio, and therefore voids can be avoided and product yields can be raised.
These and other objects of the claimed invention will be apparent to those of ordinary skill in the art after having read the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.